Semiconductor Engineering

Dissolving The Barriers In Multi-Substrate 3D-IC Assembly Design

Advanced packaging continues to promise improved form factor, cost, performance, and functionality compared to the traditional transistor scaling on SoCs. This is done by integrating multiple dies on ...
Semiconductor Engineering

Secure Physical Design Roadmap Enabling End-To-End Trustworthy IC Design Flow

The FICS Research Institute (University of Florida) has published a new research paper titled “Secure Physical Design.” This is the first and most comprehensive research work done in this area that ...
Business Wire

TSMC and Cadence Collaborate to Deliver AI-Driven Advanced-Node Design Flows, Silicon-Proven IP and 3D-IC Solutions

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it is collaborating with TSMC to enhance productivity and optimize product performance for AI-driven ...
Business Wire

Cadence and Samsung Foundry Collaborate to Certify RFIC Design Reference Flow on 8nm Process Technology

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Samsung Foundry has certified an 8nm RFIC design reference flow to develop 5G RFICs for use with sub ...